The present invention disclosed herein relates to semiconductor devices and methods of fabricating the same, and, more particularly, to multi-layer nonvolatile memory devices and methods of fabricating the same.
Semiconductor devices have, generally, reached the limit of reducing a horizontal size thereof, and, thus, a three-dimensional structure with a plurality of cell array layers stacked has been researched to overcome such a limit.
To form a cell array layer in a multi-layer, a plurality of semiconductor layers may be formed on a semiconductor substrate. However, there may be a limit in a thickness of a semiconductor layer compared to a thickness of a semiconductor substrate, and, therefore, a device formed on a semiconductor substrate may be different from a device formed on a semiconductor layer in the uniformity of their property.
FIG. 1 is a cross-sectional view of a conventional multi-layer nonvolatile memory device.
Referring to FIG. 1, a nonvolatile memory device may be formed in a NAND cell array structure. The NAND cell array structure includes a ground select line GSL and a string select line SSL that cross over a plurality of parallel active regions, and a plurality of word lines WLn. The word lines are disposed between the ground select line GSL and the string select line SSL to cross over the active regions. The ground select line GSL, the string select line SSL, and the word lines WLn are disposed mirror-symmetrically in a cell array.
An n-well region 12 and a p-well region 14 surrounded by the n-well region 12 are formed in a semiconductor substrate 10. A plurality of p-well regions 14 may be formed in a first cell array region, and the p-well regions 14 may be isolated by the n-well region 12.
The ground select line GSL and the string select line SSL may include a select gate 18s formed on a gate insulating layer 16, and a mask pattern 20s may be formed on the select gate 18s. The word line WLn may include a gate electrode 18w formed on the gate insulating layer 16 and a mask pattern 20w formed on the gate electrode 18w. The gate insulating layer 16 may be a tunnel insulating layer in a floating gate type nonvolatile memory device, or may be a multi-layered charge trap layer in a charge trap type nonvolatile memory device.
At least one semiconductor layer 26 may be formed over the semiconductor substrate 10, and a second cell array region may be formed on the semiconductor layer 26. The second cell array region may have the same disposition structure as the cell array region formed on the semiconductor substrate 10. For example, the ground select line GSL and the string select line SSL may include a select gate 30s formed on a gate insulating layer 28, and mask pattern 32s may be formed on the select gate 30s. The word line WLn may include a gate electrode 30w formed on the gate insulating layer 28 and a mask pattern 32w formed on the gate electrode 30w. The gate insulating layer 28 may be a tunnel insulating layer in a floating gate type nonvolatile memory device, or a multi-layer charge trap layer in a charge trap type nonvolatile memory device.
An interlayer insulating layer 22 is interposed between the semiconductor layer 26 and the semiconductor substrate 10. Although not shown, an interlayer insulating layer is interposed between the semiconductor layer 26 and another semiconductor layer. The semiconductor layer 26 may be crystal-grown from a semiconductor plug 24 that penetrates the interlayer insulating layer 22 depending on the method of forming the semiconductor layer 26. The semiconductor plug 24 may be an epitaxial layer crystal-grown from another semiconductor layer or semiconductor substrate thereunder.
Generally, a cell array of a nonvolatile memory device may be divided into a plurality of erase blocks, and the erase blocks are divided into p-well regions isolated by an n-well region. The erase blocks may have a predetermined potential in an operating process. Therefore, it may be desirable for a resistance of the p-well regions to be uniform for the uniformity of a bias applied to memory cells.
As illustrated, because the semiconductor layer 26 is formed over the second cell array region, its thickness may be limited due to the property degradation of the transistors formed thereunder. Therefore, a well region formed in the semiconductor layer 26 may have a limit in increasing its depth, compared to the thick semiconductor substrate 10. Consequently, there may be a difference between a well region formed in the semiconductor layer 26 and a well region formed in the semiconductor substrate 10. In addition, the well region formed in the semiconductor layer 26 may have a relatively high electrical resistance, and, thus, dispersion of a memory cell transistor characteristics may increase.